The present invention relates broadly to an A/D converter correction apparatus, and in particular, to an offset correction apparatus for a successive approximation A/D converter.
In the prior art, the offset correction loop has been employed to maintain a constant, preset offset voltage that is referred to the input of the successive approximation analog to digital convertor apparatus. A half least significant bit (LSB) offset voltage is normally required (referred to the analog input of the A/D) to reduce quantizing errors at low level analog inputs. The offset correction circuit will correct for any low frequency, temperature related offsets internally generated in the successive approximation A/D converter apparatus. However, it will also correct for any low frequency offsets present at the analog input of the successive approximation A/D converter. The time constant of the correction loop is chosen to be long compared to the frequency of the analog signal being converted. This insures stable closed loop operation of the correction loop.
The conventional prior art offset correction circuit for successive approximation A/D converters rely on field effect transistor (FET) switches to break the closed loop operation of the A/D converter and sum in a correction voltage (V.sub.c) proportional to offsets either at the analog input or in the elements in the successive approximation A/D converter. The switching transients in the field effect transistor switches vary with temperature. These transients and the stray capacitance associated with the switches introduce an output offset voltage related to the duty cycle of the offset correction loop. In addition, any output offset voltage variation in the internal converter will not be corrected, since the FET switches will switch the internal D/A converter out of the loop during offset correction. In the prior art, the best offset correction that could be achieved over a 0.degree. C. to 70.degree. C. temperature range, is about .+-.10 mv DC when using the aforementioned conventional offset correction loop and standard A/D components. For an A/D converter whose least significant bit is less than 40 mV, a .+-.10 mV variation over temperature is not acceptable.